A full adder based methodology for scaling operation in residue number system

A systematic methodology for designing full-adder-based architectures in residue number system for scaling operation and its software tool development, are introduced. Starting from the mathematical description of scaling operation in RNS, we end up with the VHDL description of a full-adder based architecture. The proposed tool was implemented in C++ language and it is available for PC and HP platforms. The derived architectures are characterized by smaller hardware complexity and higher throughput rates than existing ones.