An implementation of IEEE 1149.1 to avoid timing violations and other practical in-compliance improvements

An implementation of the IEEE 1149.1 standard, commonly called the JTAG (Joint Test Action Group) standard and created to address the time and cost issues associated with developing digital systems, is presented in this paper. Rules are given for removing gated clocks, registering all the TAP controller outputs, and daisy-chaining the boundary-scan cell clocks, resets, and control signals in a direction opposite to that of TDI to TDO signal. Several major advantages are obtained as a result of these implementation rules. Timing issues that occur while shifting between the boundary cells when the design is in layout are eliminated. During EXTEST instruction execution, skew is introduced between the toggling pad outputs to minimize damaging power spikes. Due to the elimination of the gated clocks, scan can be inserted without additional DFT logic. A method for inserting scan is given which mostly eliminates timing issues during shifting. Since the TAP controller outputs are fully registered and the gated clocks are recommended to be enables, more observe and control locations are available for an ATPG tool to easily create a high fault coverage pattern for the JTAG logic.