Improving dv/dt Immunity of Reverse Blocking IGCT for Hybrid Line-Commutated Converter

The d v /d t induced turn- on is an undesirable triggering event of integrated gate-commutated thyristor (IGCT). In this letter, we aim to improve the d v /d t immunity of the IGCT in the hybrid line-commutated converter (H-LCC), which is a newly proposed topology that can reduce the commutation failure probability. First, the mechanism of the d v /d t induced turn- on is revealed. Second, it is proved evidentially that both the d v /d t applied time and the temperature significantly impact the d v /d t immunity. Third, three distinct snubber topologies to improve the d v /d t immunity are proposed and compared based on the above analysis. It is experimentally demonstrated that the topology comprising a capacitor, resistor, and normally on junction field effect transistors (JFETs) is the most effective; the d v /d t immunity at 50 °C is improved from 144 to 655 V/ μ s when the d v /d t applied time is 5 μ s, satisfying all requirements of the H-LCC successfully.