Development of integrated heterostructures on silicon by MBE

The semiconductor industry is facing the challenge of scaling of the gate dielectric of Si CMOS devices, which are continually being made smaller. Presently SiO/sub 2/ is being used, but at thickness below 20/spl Aring/, it suffers from high tunneling leakage current and reliability problems. Altern...

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Hauptverfasser: Droopad, R., Curless, J.A., Yu, Z., Jordan, D.C., Liang, Y., Overgaard, C.D., Li, H., Eschrich, T., Craigo, B., Eisenbeiser, K.W., Finder, J., Hu, X., Wei, Y., Edwards, J., Ramdani, J., Tisinger, L., Demkov, A., Moore, K., Marshall, D., Ooms, W.J., Prendergast, J.
Format: Tagungsbericht
Sprache:eng
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Zusammenfassung:The semiconductor industry is facing the challenge of scaling of the gate dielectric of Si CMOS devices, which are continually being made smaller. Presently SiO/sub 2/ is being used, but at thickness below 20/spl Aring/, it suffers from high tunneling leakage current and reliability problems. Alternative high-k materials to replace SiO/sub 2/ need to be developed as soon as possible. The alkaline earth oxides such as barium strontium titanate (Ba/sub x/Sr/sub 1-x/TiO/sub 3/) have a substantially higher dielectric constant and are ideal candidates for gate dielectrics. Because of the higher dielectric constant a physically thicker layer can yield an equivalent oxide thickness of
DOI:10.1109/MBE.2002.1037752