A chip set core for image compression

A chip set core for image compression

Two components for image compression which provide almost all the computational power required by today's efficient codecs for full motion image compression are presented. The first component computes 8*8 discrete-cosine transform and zigzag conversion of coefficient scanning for a pixel rate u...

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Veröffentlicht in:IEEE transactions on consumer electronics 1990-08, Vol.36 (3), p.395-402
Hauptverfasser: Artieri, A., Colavin, O.
Format: Artikel
Sprache:eng
Schlagworte:
Discrete cosine transforms
Image coding
Image communication
Image storage
Microelectronics
Motion compensation
Motion estimation
Predictive coding
Standardization
Very large scale integration
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Zusammenfassung:Two components for image compression which provide almost all the computational power required by today's efficient codecs for full motion image compression are presented. The first component computes 8*8 discrete-cosine transform and zigzag conversion of coefficient scanning for a pixel rate up to 27 MHz. The second component computes full-search motion estimation for a pixel rate up to 18 MHz. System implementation for image compression is discussed.< >
ISSN:0098-3063
1558-4127
DOI:10.1109/30.103150