A hybrid Nb/CMOS integration process for superconducting tunnel junction imaging arrays

A process for hybrid superconductor/CMOS integration was developed for the fabrication of extremely sensitive color-imaging arrays using superconducting tunnel junctions. A Nb-AlO/sub x/-Nb process was used to fabricate arrays of junctions directly on top of CMOS devices. The CMOS wafers required the development of a planarization process suitable for subsequent tunnel-junction fabrication. The process involved the deposition of a sacrificial oxide layer by electron cyclotron resonance plasma-enhanced chemical vapor deposition, chemical-mechanical polishing, and a layer of spin-on glass. A process was also developed for via contacts through the oxide layer that optimized the stability of the contacts. The critical current spreads of the arrays (50 junctions) were as small (spread about 1% for 3 /spl mu/m /spl times/ 3 /spl mu/m junctions) as on bare silicon wafers.