Implementation of DVB-RCS turbo decoder for satellite on-board processing

The objective of the present paper is to provide a description of a turbo decoding algorithm for turbo codes standardised for DVB-RCS. It also presents the associated design architecture implemented in very high speed integrated circuit hardware description language (VHDL), as well as synthesis on a...

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Bibliographische Detailangaben
Hauptverfasser:	Bartolazzi, A., Cardarilli, G., Del Re, A., Giancristofaro, D., Re, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuit testing Decoding Digital video broadcasting Field programmable gate arrays Hardware design languages Integrated circuit synthesis Satellites System testing Turbo codes Very high speed integrated circuits
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Beschreibung
Zusammenfassung:	The objective of the present paper is to provide a description of a turbo decoding algorithm for turbo codes standardised for DVB-RCS. It also presents the associated design architecture implemented in very high speed integrated circuit hardware description language (VHDL), as well as synthesis on a specific field programmable gate array (FPGA). The decoding structure was tested using a rapid prototyping system based on high-density Xilinx FPGAs.
DOI:	10.1109/OCCSC.2002.1029065