Combining Relaxation With NCLX for Enhanced Optimization of Asynchronous Null Convention Logic Circuits

Quasi-Delay Insensitive (QDI) asynchronous circuits, such as NULL Convention Logic (NCL), are being utilized more and more in industry to mitigate timing issues associated with process, voltage, and temperature (PVT) variations, which are making timing closure for synchronous circuits more problematic as transistor feature size continues to shrink. This paper combines aspects of relaxation optimization with utilizing the NCL_X architecture for select portions of the circuit, resulting in an integrated optimization method for NCL circuits that achieves an average speedup of 6.8% to 12.5%, using on average 24.6% fewer to 3.7% more transistors, compared to existing NCL synthesis and optimization methods.