Cryogenic Hysteresis in 110 nm Bulk Silicon MOSFETs for Capacitorless Memory Applications

In this letter, we characterize the commercial 110nm bulk silicon MOSFETs down to 6 K, with a focus on cryogenic capacitorless memory applications. The substrate-induced steep subthreshold swing (SS) and hysteretic loop are observed at low temperatures. At 6K with V D = 1.8 V, the minimum SS is 0.2 V wide with a ~10 8 ratio of high to low drain current states. For the first time, we demonstrate the cryogenic capacitorless memory operation of bulk silicon MOSFETs. It shows a ~12 μA sense margin, long retention time (on the scale of minutes when T ≤30 K), and high write and read endurance. These features make it promising as a compact capacitorless single-transistor memory for low-temperature applications.