A robust high voltage Si LDMOS model extraction process to achieve first pass linear RFIC amplifier design success

A robust high voltage Si LDMOS model extraction process to achieve first pass linear RFIC amplifier design success

A robust model extraction procedure was developed for a high voltage Si LDMOS RFIC process to achieve first pass linear RFIC amplifier design success. The model extraction process utilizes pulsed isothermal small-signal S-parameter measurements and extracted large-signal root models at three differe...

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Bibliographische Detailangaben
Hauptverfasser: Pla, J.A., Bridges, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Integrated circuit modeling
Isothermal processes
Power system modeling
Pulse amplifiers
Pulse measurements
Radiofrequency integrated circuits
Robustness
Scattering parameters
Temperature
Voltage
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Beschreibung
Zusammenfassung:A robust model extraction procedure was developed for a high voltage Si LDMOS RFIC process to achieve first pass linear RFIC amplifier design success. The model extraction process utilizes pulsed isothermal small-signal S-parameter measurements and extracted large-signal root models at three different temperatures to extract model parameters for Motorola's Electro-Thermal (MET) FET analytical model. Large-signal model validation was performed against loadpull measurements under 1-tone and 2-tone stimuli. Also, the models were developed into a design kit within Agilent/sup R/ EEsof/sup R/'s ADS/sup R/ (Advanced Design System) to design a wide-band 30 Watt power amplifier IC which achieved first pass design success.
ISSN:0149-645X
2576-7216
DOI:10.1109/MWSYM.2002.1011607