A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors

A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors

In this paper we present a new circuit technique making standard CMOS digital circuits able to operate at a power supply voltages below 1 V. This technique is based on lowering the effective transistor threshold voltages by the use of floating-gates, where all the floating gate voltages on the chip...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Hovin, M., Wisland, D., Berg, Y., Lande, T.S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS digital integrated circuits
CMOS process
Consumer electronics
Digital circuits
Doping
Informatics
MOS devices
MOSFETs
Power supplies
Threshold voltage
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Beschreibung
Zusammenfassung:In this paper we present a new circuit technique making standard CMOS digital circuits able to operate at a power supply voltages below 1 V. This technique is based on lowering the effective transistor threshold voltages by the use of floating-gates, where all the floating gate voltages on the chip are simultaneously programmed by the use of ultra-violet light. A sinc/sup 2/ decimator is implemented in an AMS 0.6 /spl mu/m process by this technique.
DOI:10.1109/ISCAS.2002.1010724