A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies
A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can...
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| creator | Lien, W.Y. Yeh, W.G. Li, C.H. Tu, K.C. Chang, I.H. Chu, H.C. Liaw, W.R. Lee, H.F. Chou, H.M. Chen, C.Y. Chi, M.H. |
| description | A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects. |
| doi_str_mv | 10.1109/ASMC.2002.1001565 |
| format | Conference Proceeding |
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| identifier | ISBN: 9780780371583 |
| ispartof | 13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259), 2002, p.11-16 |
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| language | eng |
| recordid | cdi_ieee_primary_1001565 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Annealing Etching Isolation technology Manufacturing processes Oxidation Random access memory Semiconductor device manufacture Silicon compounds Substrates Thermal stresses |
| title | A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies |
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