A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies

A manufacturable shallow trench isolation process for sub-0.2 um DRAM technologies

A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can...

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Bibliographische Detailangaben
Hauptverfasser: Lien, W.Y., Yeh, W.G., Li, C.H., Tu, K.C., Chang, I.H., Chu, H.C., Liaw, W.R., Lee, H.F., Chou, H.M., Chen, C.Y., Chi, M.H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Annealing
Etching
Isolation technology
Manufacturing processes
Oxidation
Random access memory
Semiconductor device manufacture
Silicon compounds
Substrates
Thermal stresses
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Beschreibung
Zusammenfassung:A highly manufacturable and defect-free shallow trench isolation (STI) process is demonstrated by using 64M DRAM as a sensitive monitor. In the STI flow, a special sequence of extra anneal (1100C) after corner oxidation (i.e., liner oxide) and an RTA (1000C) anneal after HDP CVD oxide deposition can result in a significantly higher yield in 64M DRAM by effectively reducing silicon stress related substrate defects.
DOI:10.1109/ASMC.2002.1001565