On-chip structures for timing measurement and test
This paper describes the use of digitally set delay lines in conjunction with MUTEX time comparison circuits, to measure on-chip signal path timing differences to accuracies of better than 10ps. Three methods of time measurement are described. The first, which uses parallel MUTEXs with a tapped dela...
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Sprache: | eng |
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Zusammenfassung: | This paper describes the use of digitally set delay lines in conjunction with MUTEX time comparison circuits, to measure on-chip signal path timing differences to accuracies of better than 10ps. Three methods of time measurement are described. The first, which uses parallel MUTEXs with a tapped delay line, is analogous to a flash AID converter. The second one is similar to a successive approximation method. Both are fast, and efficient, but the second requires less hardware for a large number of bits. The third technique uses a MUTEX to amplify small time differences to a measurable size. Applications for these techniques include adaptive synchronization and input tests, such as data set-up time conditions that currently require the use of very expensive test hardware. We describe an on-chip method of testing these conditions, using uncorrelated signals whose statistics are known, and accurately selecting the conditions to be tested on-chip. |
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ISSN: | 1522-8681 |
DOI: | 10.1109/ASYNC.2002.1000309 |