Zynq FPGA for hardware co-simulation of Takagi-Sugeno neuro-fuzzy for MPPT algorithm incorporating sensorless wind speed estimation in grid-connected wind system

This paper presents a hardware implementation on the Field Programmable Gate Array (FPGA) Zed-Board of a Maximum Power Point Tracking (MPPT) incorporating pitch angle control system and sensorless wind speed estimation using the Takagi-Sugeno (TS) Adaptive Neuro-Fuzzy Inference System (ANFIS). The described approach is applied specifically to a grid-connected Permanent Magnet Synchronous Generator-based Variable Speed Wind Turbine (VSWT). Firstly, the paper proposes an estimator-based TS-ANFIS model for real-time wind speed estimation, addressing challenges with conventional anemometers, such as precision, and susceptibility to adverse weather conditions. The estimated wind speed guides the calculation of an optimized mechanical speed for MPPT control. Secondly, an MPPT-based TS-ANFIS controller is introduced to achieve the maximum power point, integrating pitch angle control to prevent turbine failures in high wind speeds. Finally, the paper emphasizes the hardware implementation on the FPGA Zed-Board, leveraging its parallel processing capabilities to enhance control system quality by reducing sampling periods and loop delays. Validation includes simulations in Matlab/Simulink using the Xilinx system generator and hardware co-simulation on the FPGA Zed-Board. A comparative analysis highlights the contributions and advancements of the proposed models and controllers compared to recent schemes in the field. Indeed, the proposed MPPT-based TS-ANFIS approach effectively maximizes the power extracted from the VSWT, achieving an estimated average efficiency of 99.84 %. In contrast, PID methods show average efficiencies of 92.63 %. Additionally, compared to other published works, the proposed MPPT-based TS-ANFIS method demonstrates a rapid response time of 0.001 s and lower static error at 0.02 %. Furthermore, the proposed WSE-based TS-ANFIS model exhibits superior performance and effectiveness, yielding a root mean squared error (RMSE) of 0.0085381, a determination coefficient (R2) value of 0.99985, and a Pearson correlation coefficient (r) value of 0.99996. Moreover, the proposed hardware implementation of these approaches maintains lower power usage, operating at a high frequency of 80.38 MHz and achieving a high throughput of 2572.16 Mbps.