Design methodology of a 28 nm FD-SOI capacitive feedback RF LNA based on the ACM model and look-up tables

The race to reduce the size and improve power consumption in new transistor technologies has given rise to design trade-offs that are difficult to address with standard methodologies that require an iterative process. This paper proposes a design methodology based on the ACM model and look-up tables to quickly size a 28 nm FD-SOI RF LNA that is intended to work down to 233.15 K as demonstrated with post-layout simulation results. The design incorporates different tuning knobs that might be useful for allowing the circuit to work at cryogenic temperatures during experimental measurements, ultimately allowing the circuit to work down to 4 K for quantum device measurements.