Exploring the feasibility of selective hardening for combinational logic
In this work we introduce a cost-aware methodology for selective hardening of combinational logic cells, which provides a list of the most effective candidates for hardening. Two heuristics are proposed in order to define when selective hardening becomes unfeasible. The methodology and the heuristic...
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| Veröffentlicht in: | Microelectronics and reliability 2012-09, Vol.52 (9-10), p.1843-1847 |
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| container_issue | 9-10 |
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| container_title | Microelectronics and reliability |
| container_volume | 52 |
| creator | Pagliarini, S.N. dos Santos, G.G. de B. Naviner, L.A. Naviner, J.-F. |
| description | In this work we introduce a cost-aware methodology for selective hardening of combinational logic cells, which provides a list of the most effective candidates for hardening. Two heuristics are proposed in order to define when selective hardening becomes unfeasible. The methodology and the heuristics are applied to a set of benchmark circuits using costs extracted from an actual standard cell library. The results then show that both heuristics might be appropriate for different scenarios. |
| doi_str_mv | 10.1016/j.microrel.2012.06.042 |
| format | Article |
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| subjects | Applied sciences Circuit properties Computer Science Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Hardware Architecture Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | Exploring the feasibility of selective hardening for combinational logic |
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