Exploring the feasibility of selective hardening for combinational logic

In this work we introduce a cost-aware methodology for selective hardening of combinational logic cells, which provides a list of the most effective candidates for hardening. Two heuristics are proposed in order to define when selective hardening becomes unfeasible. The methodology and the heuristics are applied to a set of benchmark circuits using costs extracted from an actual standard cell library. The results then show that both heuristics might be appropriate for different scenarios.