Large Periphery GaN HEMTs Modeling Using Distributed Gate Resistance

This paper reports on a new method to extract the intrinsic two‐port characteristics of a high‐electron‐mobility‐transistor considering the gate resistance distributed nature knowing the gate metal sheet resistance. The procedure is straightforward. It consists of de‐embedding the extrinsic parasitic elements and access resistances, measure the gate metal sheet resistance and finally extracts the intrinsic parameters by a proposed set of direct equations. It can be integrated into most modeling approaches using electrical equivalent schematics. This original method is experimentally conducted on AlGaN/GaN MOSHEMTs on Si substrate featuring four different gate widths W (0.25, 0.5, 1, 2 mm). The interest of such an extraction procedure is shown for devices with gate width above 500 μm, which indicates its strong relevance for the modeling of large GaN transistors for power electronics. In the case of fT and fmax, the classical model has variation up‐to 17.5% and 9.2% with respect to measurement while the distributed model has only 2.8% and 1.3%, respectively at W = 2 mm, which emphasized the significance of the distributed gate resistance model for large periphery GaN HEMTs devices. This paper reports on a new method which consider distributed nature of gate resistance to model large periphery GaN HEMTs. It brings significant improvement in fT and fmax modeling as compared to classical gate resistance modeling for large gate width above 500 um. This further highlights the interest of considering the distributed gate resistance on the performance of the GaN transistor.