A Continuous Semi-Empirical VJFET Capacitance Model from Sub to above Threshold Regime

This paper presents and discusses the depletion mechanisms that dominate in a TSI-VJFET under different bias conditions as expressed by the gate-source (CGS) and gate-drain (CGD) capacitances. It is shown that at pinch off the dominant capacitance is the drift capacitance and that in conduction the drain source voltage plays a significant role in channel’s formation. Furthermore a semi empirical capacitance model is introduced. CGS and CGD are modeled below and above threshold voltage by considering parallel plate capacitors with different plate configuration in te two cases. Then, the derived expressions are unified using a transition function that preserves the continuity of the model. The model was adjusted and fitted adequately to measured CV data from fabricated TSI-VJFET.