A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOS: Invited

Clique-based neural networks implement low-complexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low-energy budget. However, the implementation in the state of the art is not flexible and a fabricated circuit is...

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Veröffentlicht in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2018-12, Vol.66 (5), p.1-12
Hauptverfasser: Larras, Benoit, Chollet, Paul, Lahuec, Cyril, Seguin, Fabrice, Arzel, Matthieu
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Sprache:eng
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Zusammenfassung:Clique-based neural networks implement low-complexity functions working with a reduced connectivity between neurons. Thus, they address very specific applications operating with a very low-energy budget. However, the implementation in the state of the art is not flexible and a fabricated circuit is only usable in a unique use case. Besides, the silicon area of hardwired circuits grows exponentially with the number of implemented neurons that is prohibitive for embedded applications. This paper proposes a flexible and iterative neural architecture capable of implementing multiple types of clique-based neural networks of up to 3968 neurons. The circuit has been integrated in an ST 65-nm CMOS ASIC and occupies a 0.21-mm 2 silicon surface area. The proper functioning of the circuit is illustrated using two application cases: a keyword recovery application and an electrocardiogram classification. The neurons outputs are updated 83 ns after a stimulation, and a neuron needs an energy of 115 fJ to propagate a change at the input to its output.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2018.2881508