Power-Handling Capacity and Nonlinearity Analysis for Distributed Electronic Impedance Synthesizer

With advantages of small size, light weight, and fast tuning capability, electronic impedance synthesizer (EIS) presents game-changing opportunities for industry. However, their widely acceptance is still restrained by the understanding of power-handling capacity and linearity issues. This work addresses both issues through the development of a voltage distribution theory which enables simulating voltage at the position of every PIN diode in the distributed EIS. It provides a way of understanding and predicting the power-handling capacity and nonlinearity of EIS from its linear region. As an example of validation for this theory, a 12-bit EIS along with an automatic measurement setup is presented. Experimental results show a good match among measurement, simulation, and analytical model. The 1 dB compression point (P1dB) of the EIS is larger than 35 dBm, and the third-order input intercept point is larger than 57 dBm. Since the proposed theory is validated, it is possible to be used as a criterion in the optimization process to enhance the power-handling capacity and linearity. Potential applications of such high-linearity EIS can be found in Load-Pull systems, noise measurements, variable impedance loads, tunable matching networks, reconfigurable components, and so on.