A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip

In this paper, we present a Model Driven Engineering (MDE) methodology for facilitating the modeling of the partial reconfiguration process, and for implementing Dynamic Reconfigurable System-on-Chip (DRSoC). The rationale for this approach is to provide a modeling front-end that enables to visually compose a hardware platform, containing heterogeneous components, using both static and context-management hardware wrappers. A model transformations engine (MTE) processes the high-level models to obtain the inputs for the Xilinx dynamic partial reconfiguration (DPR) design flow, with the benefit of better exploiting and reusing the designer intentions regarding the allocation of tasks into reconfigurable areas. Furthermore, the automatic synthesis of a reconfiguration controller (RecOS) with context-management and task relocation capabilities is supported in this version of our tool. The latter feature is possible due to the integration of relocation tool OORBIT into the design chain, but we point out at other avenues of research. We present a case study in which we assess the benefits of the methodology and present a thorough analysis of the reconfiguration costs associated with the context and relocation management, showing speedups of 1.5x over other solutions. •This paper presents a UML MARTE based methodology for modeling Dynamically Reconfigurable SoCs.•The methodology and tools presented here in are built upon the IP-XACT standard to foster reuse.•Context-management wrapper enables task distribution, scheduling and preemption.•The approach enables to seamlessly create and automatically generate DRSoCs.•The reconfiguration process is catered through the generation of a reconfiguration controller.