Design considerations of CMOS active inductor for low power applications

Previous studies have shown that g m / I D (transconductance-to-drain-current) ratio based design is useful for optimizing analog circuits. In this paper, we explore challenges associated with designing a low-power active inductor. We focus in particular on sizing issues that arise as the transistor speed is maximized and the current consumption is minimized. Finally, we apply the results to design an amplifier integrated with an active inductor in 0.18 μ m CMOS process and show that by systematically working through sizing issues, a 10 μ A sub GHz amplifier can be designed.