Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD

A novel multi-ASIP and network-on-chip (NoC) based flexible architecture for parallel iterative demapping with turbo decoding using signal space diversity (TBICM-ID-SSD) is presented in this brief. The proposed heterogeneous multi-ASIP architecture uses multiple instances of two types of application-specific instruction-set processor (ASIP): one dedicated for turbo decoding and the second for demodulation, besides butterfly-topology-based NoCs. This architecture presents novel and outstanding levels of flexibility and scalability in the design of advanced iterative receivers. It supports modulation schemes from BPSK to 256-QAM for any mapping style and supports 8 state single and double binary turbo codes used in 3GPP-LTE, DVB-RCS, and WiMAX. FPGA prototyping results are presented, and the extra hardware cost required to enable turbo demodulation is evaluated.