VLS Grown 4H-SiC Buried P+ Layers for JFET Lateral Structures

Lateral JFET transistors have been fabricated with N and P-type channels tentatively integrated monolithically on the same SiC wafer. Buried P+ SiC layers grown by Vapor-Liquid-Solid (VLS) selective epitaxy were utilized as source and drain for the P-JFET and as gate for the N-JFET. The ohmicity of...

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Veröffentlicht in:	Materials science forum 2015-06, Vol.821-823, p.789-792
Hauptverfasser:	Sejil, Selsabil, Brylinski, Christian, Morel, Hervé, Carole, Davy, Ferro, Gabriel, Lazar, Mihai, Planson, Dominique, Raynaud, Christophe, Laariedh, Farah
Format:	Artikel
Sprache:	eng
Schlagworte:	Electric power Engineering Sciences
Online-Zugang:	Volltext
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