Theoretical study and optimisation of a standard deviation estimator circuit for adaptive threshold spike detection

Summary This paper presents a theoretical study and the resulting architecture of an analogue‐based standard deviation (SD) estimator, typically used in biomedical spike detectors to assess the noise level of bioelectrical recordings online. This well‐known circuit generated a significant inaccuracy, so the aim was to increase the efficiency of spike detection through proper calculation of the noise SD, by developing a rigorous, original theoretical study. The approach consisted of establishing behavioural models for the SD estimation circuit to obtain a transfer function and compare different controllers. This modelling approach also highlighted the parameters available and the impact of their relationships on design optimisation. The behavioural models, inherently based on approximations, were then initially validated by comparing them with actual circuit behaviour, obtained using discrete components. These comparisons revealed that the models matched the actual circuit measurements. Finally, taking into account the conclusions of our theoretical study, an integrated version of this adaptive threshold spike detector was designed using 0.35‐µm complementary metal–oxide–semiconductor technology. Simulations of this circuit revealed that the proposed controller eliminated the static error and ensured efficient spike detection. Copyright © 2016 John Wiley & Sons, Ltd. This paper studies a circuit estimating the standard deviation of the noise in electrophysiological recordings, before threshold‐based spike detection. Its behaviour is nonlinear and stochastic. This article proposes for the first time a thorough modelling of this circuit. Two models are developed: one, nonlinear, reproduces accurately and quickly the circuit behaviour; the other, linear, provides a transfer function, with analytic expression of circuit performances, based on design parameters, which allows the rational sizing of the loop controller. Thus, an integrated implementation of this circuit is proposed and simulated.