Gate-last integration on planar FDSOI for low-VTp and low-EOT MOSFETs

[Display omitted] •We integrated a gate-last on high-k first on planar fully depleted SOI MOSFETs.•pMOSFETs reach a low threshold voltage of VTp=−0.2V.•Gate-last pMOSFETS present one decade gate current gain compared to gate first ones.•The use of a TiN MOCVD capping decreases the EWF by 0.2eV and degrades the reliability compared to TiN ALD.•EOT down to 0.8nm with midgap TaN are obtained on HfO2 in a high-k last integration. We integrated planar fully depleted (FD) SOI MOSFETs with a gate-last on high-k first (GL-HKF) down to gate lengths of Lg=15nm and active widths of W=80nm. Such an integration scheme enables reaching for pMOSFETs a threshold voltage of VTp=−0.2V and one decade gate current (JG) gain, as well as similar hole mobility and ON-currents, compared to pMOSFETs integrated with a gate first. This approach is also benchmarked with high-k last (GL-HKL) stacks in terms of leakage, equivalent oxide thickness (EOT), effective work-function (EWF) and flat band voltage (VFB) shift under stress.