DC and low frequency noise performances of SOI p-FinFETs at very low temperature

•The benefit of the use of strain engineering techniques is kept at 10K operation.•The carrier number fluctuations dominate the 1/fγ noise in weak inversion. The γ parameter variation with the temperature (independent from strain and gate length) shows that the spatial distribution of traps in the oxide is not homogenous and that the active trap density increases towards the interface.•The access resistance noise contribution on the total noise, which prevail in strong inversion operation, originates from mobility fluctuations at 300K while at 10K seems to have a trapping - detrapping origin. In this paper, DC and noise measurements on strained and unstrained SOI p-FinFETs were performed at cryogenic temperatures (10K) in order to evaluate the device performances and study the low frequency noise mechanisms. The main electrical parameters (threshold voltage, subthreshold swing, mobility, etc.) are investigated and compared to those found at 80K and 300K. The low frequency noise analysis clearly shows that from 300K to 10K, the carriers number fluctuation dominates the flicker noise in the channel in weak inversion, while the access resistances noise contribution prevails in strong inversion. 1/fγ noise has been observed with γ varying with the temperature, which implies a non-uniformity of the active trap density in the oxide depth. The noise of the access resistances at 300K originates from mobility fluctuations, while at low temperature operation it seems to have a trapping–detrapping origin.