Study of Porous SiOCH Patterning Using Metallic Hard Mask: Challenges and Solutions
The choice of copper/low-k interconnect architectures is instrumental in achieving high device performances. Today, the implementation of porous low-k materials becomes mandatory in order to compensate metal resistance increase upon RC product. However, their introduction, which was initially planne...
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| Veröffentlicht in: | ECS transactions 2011-01, Vol.35 (4), p.667-685 |
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| creator | Posseme, Nicolas David, Thibaut Chevolleau, Thierry Darnon, Maxime Bailly, Fanny Bouyssou, Regis Ducote, Julien Chaabouni, Hamed El Kodadi, Mohamed Licitra, Christophe Verove, Christophe Joubert, Olivier |
| description | The choice of copper/low-k interconnect architectures is instrumental in achieving high device performances. Today, the implementation of porous low-k materials becomes mandatory in order to compensate metal resistance increase upon RC product. However, their introduction, which was initially planned for the 65nm technological node, was delayed to 45nm node due to integration issues. Using an integration strategy which combines porous SiOCH materials and metal hard masks, the difficulties and possible solutions are presented in this paper with emphasis on plasma etching. |
| doi_str_mv | 10.1149/1.3572312 |
| format | Article |
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| ispartof | ECS transactions, 2011-01, Vol.35 (4), p.667-685 |
| issn | 1938-5862 1938-6737 |
| language | eng |
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| source | IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link |
| subjects | Physics |
| title | Study of Porous SiOCH Patterning Using Metallic Hard Mask: Challenges and Solutions |
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