Study of Porous SiOCH Patterning Using Metallic Hard Mask: Challenges and Solutions

The choice of copper/low-k interconnect architectures is instrumental in achieving high device performances. Today, the implementation of porous low-k materials becomes mandatory in order to compensate metal resistance increase upon RC product. However, their introduction, which was initially planned for the 65nm technological node, was delayed to 45nm node due to integration issues. Using an integration strategy which combines porous SiOCH materials and metal hard masks, the difficulties and possible solutions are presented in this paper with emphasis on plasma etching.