DPFFs: [C.sup.2]MOS direct path flip-flops for process-resilient ultradynamic voltage scaling

We propose two master-slave flip-flops (FFs) that utilize the clocked CMOS ([C.sup.2]MOS) technique with an internal direct connection along the main signal propagation path between the master and slave latches and adopt an adaptive body bias technique to improve circuit robustness. [C.sup.2]MOS structure improves the setup margin and robustness while providing full compatibility with the standard cell characterization flow. Further, the direct path shortens the logic depth and thus speeds up signal propagation, which can be optimized for less power and smaller area. Measurements from test circuits fabricated in 130 nm technology show that the proposed FF operates down to 60 mV, consuming 24.7 pW while improving the propagation delay, dynamic power, and leakage by 22%, 9%, and 13%, respectively, compared with conventional FFs at the iso-output-load condition. The proposed FFs are integrated into an 8 x 8 FIR filter which successfully operates all the way down to 85 mV.