Analysis of the sub-surface damage of mc- and Cz-Si wafers sawn with diamond-plated wire

The usage of diamond-plated wire to produce silicon wafers for the photovoltaic industry is still a new and highly investigated wafering technology. The requirements regarding the quality of the wafer surface are very high and they have to compete with the cost effectiveness and quality of wafers produced by the established loose abrasive sawing technology. Hence, the wafer topography, the fracture stress and the corresponding sub-surface damage have to be investigated and improved. This paper discusses the topographic parameters, the crack depths and the fracture stress of mono- and multi-crystalline silicon wafers that were produced on multi-wire saws using diamond-plated wire and comparable process parameters. Especially multi-crystalline silicon (mc-Si) wafers exhibit lower fracture stress values compared to mono-crystalline silicon (cz-Si) wafers. We investigated the relations between crack depth and fracture stress. In detail, we determined a 15% higher median and a 40% increased interquartile range of the crack depth of mc-Si wafers in comparison to similar produced cz-Si wafers. That correlates with lower fracture stress values of textured mc-Si wafers compared to cz-Si wafers. In the following, we studied the sub-surface damage as a function of crystal orientation in detail. It was found that the crack depths increases from the {100} plane over the {111} plane to the {101} plane. However for the {101} plane two grains were investigated, resulting in a discrepancy of 4 m. This may be related to the unknown rotation angle between the corresponding {111} cleavage planes and the wire direction and requires further investigations.