Analysis of risks and related damages due to the implementation of virtual metrology algorithms into semiconductor fabrication lines: Presentation held at APC Conference XXIV 2012, 10.09.2012 to 12.09.2012, Michigan

Increasing wafer diameter and decreasing feature sizes demand for reliable and fast process control on wafer level and even within wafer control loops. Virtual Metrology (VM) appears to be the only way to reach the required level of control. VM enables the prediction of physical and electrical device parameters on the wafers from information collected in real time from manufacturing tools. Implementing VM algorithms into existing fab structures will permit to virtually measure all processed wafers, thus improving device quality and yield. A model has been developed to calculate the economic benefits due to the implementation of VM. This model has been extended to consider also potential damages in case the VM algorithms fail. This paper presents the evaluation of potential risks due to the implementation of VM algorithms into existing fabrication lines, providing a valuable and important extension of existing investment assessment.