BICUBIC INTERPOLATION CIRCUIT BASED ON FPGA

The invention provides a bicubic interpolation circuit based on an FPGA (Field Programmable Gate Array), and the working mode of the circuit is as follows: firstly, a control unit reads pixels from an external DDR (Double Data Rate) memory into an input cache through DMA (Direct Memory Access), the read pixels are circularly written into the input cache, then PE (Poly Ethylene) directly reads the input cache into an internal operation register, and after the PE calculates high-definition image pixel points, the high-definition image pixel points are output through an output cache. And the output of the PE is rearranged, so that the hardware output is directly connected with a high-definition video interface. According to the method, the number of line caches is reduced, the calculation amount of each time period is improved, the throughput is maximized, and the delay time required by calculation is reduced; and an output cache is designed, so that the system can be butted with a conventional video interface.