MEMORY CONTROL DEVICE WITH AN EQUIPMENT PERFORMING IN ALTERNATING MANNER THE PROCESSING OF MEMORY CLAIMS BY MEANS OF WAITING LINES

A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.