MEMORY CONTROL UNIT PROVIDING OPTIMAL TIMING OF MEMORY CONTROL SEQUENCES BETWEEN DIFFERENT MEMORY SEGMENTS

A memory controller (310) is described that comprises individual control segments (311a, 311b) for controlling memory (312) that is divided into individual pairs of memory segments (312a, 312b). The programmable memory controller (310) provides improved average access times for memory devices (312) by reducing the number of wait cycles between memory operations (Fig. 4). A common data bus (319) is shared between the memory segments (312a, 312b). Each control segment (311a, 311b) provides individual sets of addresses (318, 336) and control lines (320, 322, 324, 326, 338, 340, 342, 344) to each memory segment (312a, 312b) so that control sequences (Fig. 4) can occur simultaneously between multiple control (311) and memory segments (312). Accordingly, when a control sequence (Fig. 4) is in process within one segment (311a, 312a) another control sequence (Fig. 4) can occur simultaneously in another segment (311b, 312b). By overlapping control sequences (Fig. 4) in this fashion, the bandwidth of the data bus (319) is increased by remaining idle less frequently. Each control segment (311a, 311b) provides a plurality of allow mode signals to the other control segment. The allow mode signals are used by a request selector (530) to select a memory request from a plurality of pending memory requests (303), such that the selected request (552) can begin as soon as one of the control segments (311a, 311b) is ready to accept such a request. L'invention décrit un gestionnaire de mémoire (310) qui comprend des segments individuels de commande (311a, 311b) pour la gestion de la mémoire (312) qui est partagée en paires individuelles de segments de mémoire (312a, 312b). Le gestionnaire de mémoire programmable (310) obtient des temps d'accès moyens améliorés aux dispositifs de mémoire (312) en réduisant le nombre de cycles d'attente entre les opérations de la mémoire (figure 4). Un bus commun de données (319) est partagé entre les segments de mémoire (312a, 312b). Chaque segment de commande (311a, 311b) obtient des ensembles individuels d'adresses (318, 386) et des lignes de commande (320, 322, 324, 326, 338, 340, 342, 344) à chaque segment de mémoire (312a, 312b) si bien que des séquences de commande peuvent survenir simultanément entre le dispositif de commandes multiples (311) et les segments de mémoire (312). De ce fait, quand une séquence de commande est en cours de traitement dans un segment (311a, 312a), une autre séquence de commande (figure 4) peut survenir simultan