SYSTEM AND METHOD FOR MODEL-BASED VERIFICATION OF LOCAL DESIGN RULES

A system for model-based verification of local design rules comprises a processing unit, a verification database wherein a cell reference graph representing an integrated circuit design as a hierarchical collection of cells is stored, a verification function memory wherein a verification function is...

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Hauptverfasser: BAISUCK, ALLEN, GOWEN, WALTER, K., III, FAIRBANK, RICHARD, L, SALECKER, ANTON, G, HOOVER, WILLIAM, W., III, HUCKABAY, JUDITH, A, ROGOYSKI, ERIC, HENRICKSEN, JON, R
Format: Patent
Sprache:eng ; fre
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Zusammenfassung:A system for model-based verification of local design rules comprises a processing unit, a verification database wherein a cell reference graph representing an integrated circuit design as a hierarchical collection of cells is stored, a verification function memory wherein a verification function is stored, a friendly worklayer memory, and an unfriendly worklayer memory. Each cell can include shape models and references to lower-level cells. The processing unit first verifies each cell in the cell reference graph that does not reference any lower-level cells, after which the processing unit verifies each cell for which all lower-level cells referenced have been previously verified. During the verification of a selected cell, the processing unit determines whether models in the selected cell interact with other models in the selected cell or with any lower-level cell. Interacting models are referred to as being "unfriendly", and non-interacting models are referred to as being "friendly". The processing unit references a previously calculated verification result when models are friendly, and applies a verification function to models that are unfriendly. A method for model-based verification of local design rules comprises the steps of: selecting a cell for verification; selecting a verification function; determining whether models in the cell reference graph are unfriendly with a model in the selected cell; applying the selected verification function to each model involved in an unfriendly interaction; and generating an override in the event that a previously calculated verification result is invalid due to unfriendliness between models. Un système pour la vérification à base de modèles de la géométrie locale comprend une unité de traitement, une base de données de vérification dans laquelle un graphique de références de cellules représentant la géométrie d'un circuit intégré sous forme d'un ensemble hiérarchique de cellules est mémorisé, une mémoire à fonction de vérification dans laquelle une fonction de vérification est mémorisée, une mémoire de couche de travail conviviale, et une mémoire de couche de travail non conviviale. Chaque cellule peut comprendre des modèles de forme et des références à des cellules de niveau inférieur. L'unité de traitement vérifie d'abord chaque cellule dans le graphique de référence de cellules qui ne désigne pas de cellules de niveau inférieur, après quoi l'unité de traitement vérifie chaque cellule pour laquelle toutes les