CIRCUIT ARRANGEMENT FOR TESTING A SEMICONDUCTOR STORE BY MEANS OF PARALLEL TESTS WITH DIFFERENT TEST BIT PATTERNS

The invention relates to a circuit arrangement for testing a semiconductor store in which the various test bit patterns can be written into registers (REG) and into storage cell n-tuples (NSPZ) in which the test bit patterns of the registers (REG) are comparable with the bit patterns of the storage...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	LUSTIG, BERNHARD
Format:	Patent
Sprache:	eng ; ger
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES STATIC STORES TESTING
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!