MICROPROCESSOR WITH MEMORY HAVING INTERLEAVED ADDRESS INPUTS AND INTERLEAVED INSTRUCTION AND DATA OUTPUTS

MICROPROCESSOR WITH MEMORY HAVING INTERLEAVED ADDRESS INPUTS AND INTERLEAVED INSTRUCTION AND DATA OUTPUTS

A two bus (11, 13), two instruction type, pipelined microprocessor has a control means (45) which orders application of instruction (12) and data (10) addresses to a memory (19) and further interleaves instructions and data on a single bus (13) to achieve maximum efficiency in operation. Un micropro...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: KROMER, PHILIP, FREDERICK, III
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A two bus (11, 13), two instruction type, pipelined microprocessor has a control means (45) which orders application of instruction (12) and data (10) addresses to a memory (19) and further interleaves instructions and data on a single bus (13) to achieve maximum efficiency in operation. Un microprocesseur à pipeline à deux bus (11, 13) et à deux types d'instruction possède un organe de commande (45) qui ordonne l'application des adresses d'instruction (12) et de données (10) à une mémoire (19) et qui imbrique les instructions et les données sur un seul bus (13) pour obtenir une efficacité de fonctionnement maximum.