CHIP AND ELECTRONIC DEVICE

Provided in the embodiments of the present disclosure are a chip and an electronic device. The chip comprises: a plurality of chip ports, a port multiplexing logic module and a scanning test logic module, wherein the port multiplexing logic module is provided with a plurality of groups of first ports and a plurality of groups of second ports, and the plurality of chip ports are divided into a plurality of groups according to a preset granularity; each group of chip ports is connected to at least one of the plurality of groups of first ports and the plurality of groups of second ports of the port multiplexing logic module, and the plurality of groups of first ports or the plurality of groups of second ports of the port multiplexing logic module are connected to the scanning test logic module; and the port multiplexing logic module is configured to control the gating of a path between each of the chip ports and the scanning test logic module according to a control instruction and in the unit of the preset granu