THREE-DIMENSIONAL VERTICAL INTERCONNECT ARCHITECTURE AND METHODS FOR FORMING

In some embodiments, a method for forming a multiple die stack comprises forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal la...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MAITY, Nirmalya, BERKENS, Martinus Maria, PARIKH, Suketu, PRANATHARTHIHARAN, Balasubramanian, YEOH, Andrew, SUNDARRAJAN, Arvind
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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