MEMORY STRUCTURE WITH 4F 2 OPTIMIZED CELL LAYOUT

A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors that are arranged in a honeycomb pattern to maximize the available capacitor footprint on top of the memory array. The bit lines may partially intersect with bottom source/drain regions of two adjacent c...

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Bibliographische Detailangaben
Hauptverfasser: KANG, Sung-Kwan, KANG, Chang Seok
Format: Patent
Sprache:eng ; fre
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