MEMORY, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and particularly relates to a semiconductor structure, a manufacturing method therefor, a memory, and an electronic device, which are used for solving the technical problem of hole defects or slit defects of node contact interfaces of vertical channel transistors. The method comprises: providing a target substrate (100), a plurality of active pillars (110) arranged at intervals in a first direction and a second direction being formed in the target substrate (100), the plurality of active pillars (110) all extending in a third direction, and insulating layers (120) being formed between adjacent active pillars (110); and forming target conductive contact structures (20) covering the top surfaces of the active pillars (110) and target insulating structures (30) covering the top surfaces of the insulating layers (120), the adjacent target conductive contact structures (20) all being isolated by the target insulat