CLOCK SYNCHRONIZATION METHOD AND FIRST DIE

The embodiments of the present application provide a clock synchronization method and a first die, relate to the technical field of chips, and solve the problem of asynchronous clock signals of a plurality of dies in a chip system. The clock synchronization method is applied to a chip system, the chip system comprises a plurality of dies, the plurality of dies comprise a first die and a second die, and the method comprises: a first die receiving a first clock signal and a first data signal which are sent by a second die, and based on the first clock signal, sampling the first data signal to obtain a second data signal; based on a phase difference between the first clock signal and the second clock signal, the first die adjusting the phase of the first clock signal to obtain a third clock signal, wherein the second clock signal is the clock signal of the first die; and based on the third clock signal, the first die sampling the second data signal. The embodiments of the present application are used for the pro