DECODING METHOD, PROCESSOR, CHIP, AND ELECTRONIC DEVICE

Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method comprises: generating an instruction fetch request carrying at least one switching mark, the switching mark at least indicating an instruction position for decoder group switching; in response to micro-ops obtained from decoding by decoder groups, acquiring an instruction stream fetched by means of the instruction fetch request, and according to the switching mark carried in the instruction fetch request, determining the instruction position for decoder group switching; according to the instruction position, distributing the instruction stream to multiple decoder groups for parallel decoding, and carrying a switching mark in a target micro-op obtained by decoding a target instruction, the target instruction being an instruction corresponding to the instruction position; and in response to searching a micro-op cache for micro-ops, if the instruction fetch request is hit in the micro-op cac