LAYERED CERAMIC ELECTRONIC COMPONENT

Provided is a layered ceramic electronic component in which peeling between ceramic layers is prevented. This layered ceramic electronic component 10 comprises: a layered body 12 comprising a plurality of layered ceramic layers 14 and a plurality of layered inner electrode layers 16, the layered bod...

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Bibliographische Detailangaben
Hauptverfasser: USUI, Kazunori, SAWADA, Takashi
Format: Patent
Sprache:eng ; fre ; jpn
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Beschreibung
Zusammenfassung:Provided is a layered ceramic electronic component in which peeling between ceramic layers is prevented. This layered ceramic electronic component 10 comprises: a layered body 12 comprising a plurality of layered ceramic layers 14 and a plurality of layered inner electrode layers 16, the layered body including a first main surface 12a and a second main surface 12b which face each other in a layering direction x, a first side surface 12c and a second side surface 12d which face each other in a width direction y that is orthogonal to the layering direction x, and a first end surface 12e and a second end surface 12f which face each other in a length direction z that is orthogonal to the layering direction x and the width direction y; and a plurality of outer electrodes 30. The layered ceramic electronic component is characterized in that: the plurality of inner electrode layers 16 include first inner electrode layers 16a that are layered alternately with the plurality of ceramic layers 14 and that are exposed to the first end surface 12e and the second end surface 12f, and second inner electrode layers 16b that are layered alternately with the plurality of ceramic layers 14 and that are exposed to the first side surface 12c and the second side surface 12d; the first inner electrode layers 16a and the second inner electrode layers 16b are disposed spaced apart from each other, and further include dummy electrodes 40 that are exposed from one of the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d; the plurality of outer electrodes 30 comprise a first outer electrode 30a and a second outer electrode 30b that are connected to the first inner electrode layers 16a, and a third outer electrode 30c and a fourth outer electrode 30d that are connected to the second inner electrode layers 16b; and in each of the dummy electrodes 40, a region 44 that is spaced apart from an exposed portion 42 of the dummy electrode 40 by at least 50% toward the center of the layered body 12 exhibits a conductive component wire coverage of less than 50%. L'invention concerne un composant électronique en céramique stratifié dans lequel tout délaminage entre des couches de céramique est empêché. Ce composant électronique en céramique stratifié 10 comprend : un corps stratifié 12 comprenant une pluralité de couches céramiques stratifiées 14 et une pluralité de couches d'électrode interne stratifiées 16, le corps stratifié compren