METHOD AND STRUCTURE OF FORMING CONTACTS AND GATES FOR STAGGERED FET
A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separa...
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| creator | XIE, Ruilong ANDERSON, Brent CHU, Albert GUO, Dechao WANG, Junli CHOU, Anthony |
| description | A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.
Structure microélectronique comprenant une pluralité de transistors inférieurs et une pluralité de transistors supérieurs, les canaux des transistors supérieurs étant décalés par rapport aux canaux des transistors inférieurs. Un pilier diélectrique inférieur est situé sous un transistor supérieur, le pilier diélectrique séparant des transistors inférieurs. |
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| title | METHOD AND STRUCTURE OF FORMING CONTACTS AND GATES FOR STAGGERED FET |
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