METHOD AND STRUCTURE OF FORMING CONTACTS AND GATES FOR STAGGERED FET

METHOD AND STRUCTURE OF FORMING CONTACTS AND GATES FOR STAGGERED FET

A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separa...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: XIE, Ruilong, ANDERSON, Brent, CHU, Albert, GUO, Dechao, WANG, Junli, CHOU, Anthony
Format: Patent
Sprache:eng ; fre
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors. Structure microélectronique comprenant une pluralité de transistors inférieurs et une pluralité de transistors supérieurs, les canaux des transistors supérieurs étant décalés par rapport aux canaux des transistors inférieurs. Un pilier diélectrique inférieur est situé sous un transistor supérieur, le pilier diélectrique séparant des transistors inférieurs.