MEMORY AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE

Provided in the present application are a memory and a manufacturing method therefor, and an electronic device. The memory comprises a transistor, and a capacitor, which is arranged at the transistor. The capacitor comprises a plurality of conductor layers and a plurality of oxidization layers. The conductor layers and the oxidization layers are alternately arranged in a first direction away from the transistor. The capacitor further comprises channel holes, which penetrate the conductor layers and the oxidization layers. A conductor column is arranged in each channel hole. A ferroelectric layer is arranged between the conductor column and an inner wall of the channel hole. The conductor column is electrically connected to the transistor. The ferroelectric layer is electrically connected to the conductor layers. Each conductor layer forms a capacitor with an adjacent conductor column, and the capacitance values of two adjacent capacitors are equal, such that the capacitance values of storage units in the memo